For a complex digital system with multiple controlling elements and multiple controlled elements, the number of unique signal paths required for a fully connected graph-type control signal implementation increases dramatically as a function of system complexity. To avoid routing congestion, wasted area for interconnect, and long signal paths, it is desirable to share as many signal paths as possible. For example, in a system with N control units (C.sub.1, C.sub.2, C.sub.N) and M functional units (F.sub.1, F.sub.2, . . . F.sub.M) where each functional unit requires W control signals, in order to implement a system with unique control signal paths linking every control unit to every functional unit, W*N*M separate signal paths are required. If the control units share a single set of signal paths to each functional unit, then only W*M signal paths are required. However, in order to share control signals, it is necessary to have an appropriate signaling scheme and protocol in place for reliable and contention-free communication.
There are a number of signaling schemes for shared signals that have been widely used in the past including tri-state (three-state) and wired-or signaling. One problem with conventional tri-state signaling is the need to rescind an asserted control signal to prevent the controlled functional unit from recognizing the asserted control signal multiple times. Returning to the hypothetical system with N control units described earlier, a control unit C, might assert a group of control signals in cycle i, rescind those signals in cycle i+1, and then tri-state the control signals in cycle i+2. A system operating in this manner would therefore require two overhead clock cycles (cycle i+1 and cycle i+2) each time a control unit finishes asserting a control signal. The overhead can be reduced by causing the control signals to be rescinded in the first half of cycle i+1 and tri-stated in the second half of cycle i+1, but this still requires one overhead clock cycle after assertion of the control signal. Either weak pull-up/pull-down resistors or bus holder cells (weak cross-coupled inverters) can be used to hold the control signals in a negated state in the absence of control activity for an extended period of time, but if bus holder cells are used, then it may be necessary to further include an initialization step to rescind all control signals to a known, inactive state when the system is reset.
If either of the above two signaling schemes is used, and there is more than one control unit, there will be contention between the output drivers of the multiple control units attempting to assert the same control signal in consecutive clock cycles. The attempt by say a second control unit to assert control signals would contend with the rescinding of control signals by say a first control unit. This contention problem can be eliminated through the use of wired-or signaling but at the cost of DC power consumption when control signals are asserted, and potentially long periods time are required to passively rescind asserted control signals when negated. Another approach to eliminating the contention problem is to always rescind control signals in the first half of a clock cycle and design the control units to only assert control signals in the second half. This approach has the disadvantage of providing only a short time window to assert potentially long and heavily loaded signal paths. A need therefore arises for a signaling system which avoids contention between multiple control and functional units without increasing DC power consumption, without limiting assertion times for data transfer, and without imposing significant overhead delays.